live forge · round 1,285 · Kimi K2.7 Code

Watch the minions rewrite your Verilog.

PLAN reads the module, FORGE hammers lines into fewer gates, PROVE checks every change stays logically equivalent. The optimizer is a black box; the minions are real, synced to the file being edited on the left.

mux8.vupload .v

1// mux8.v - 8:1 multiplexer, 8-bit data

2module mux8 (

3 input wire [7:0] in0, in1, in2, in3,

4 input wire [7:0] in4, in5, in6, in7,

5 input wire [2:0] sel,

6 output reg [7:0] y

7);

8 always @(*) begin

9 case (sel)

10 3'd0: y = in0;

11 3'd1: y = in1;

12 3'd2: y = in2;

13 3'd3: y = in3;

14 3'd4: y = in4;

15 3'd5: y = in5;

16 3'd6: y = in6;

17 default: y = in7;

18 endcase

19 end

20endmodule

gates

—

baseline

reduction

—

fewer gates

equivalence

—

proven

PLANreads line 7

FORGErewrites line —

PROVEproves line —